1. Field of the Invention
The present invention relates to a bit line sense amplifier for a semiconductor memory device, and in particular to a bit line sense amplifier which can increase a data sensing speed and improve an operational speed of a chip by using a current sensing method in data-sensing a bit line having a large capacitive load.
2. Description of the Background Art
FIG. 1 illustrates a conventional bit line sense amplifier. As shown therein, the conventional bit line sense amplifier is a cross-coupled latch type bit line sense amplifier which senses a data according to a charge sensing method, and amplifies and outputs the data.
According to the charge sensing method, in case charge sharing takes place according to a charge conservation law in regard to charges stored in a data storage capacitor of a memory cell selected by bit lines BL, /BL having a half VCC voltage (approximately 1/2 VCC) level due to equalization and precharge, a small voltage difference (at most, a few hundreds mv) is generated between the bit line pair BL, /BL.
Thereafter, the bit line sense amplifier senses the voltage difference, controls and amplifies the sensed voltage difference according to sense amp driving signals RTO, /SE, and outputs it to a data bus line. At the same time, the bit line sense amplifier writes back the same data in the data storage capacitor of the selected memory cell.
In the charge sensing method, a great capacitive load is applied to a sense amp line and the bit lines BL, /BL during a sensing operation, and thus a delay is often generated when the small voltage difference is amplified and outputted to an output terminal.
This phenomenon increases an access time in a high-speed memory device, thereby reducing an output speed of the data.